data brief for further information contact your local stmicroelectronics sales office. october 2011 doc id 022383 rev 1 1/5 5 STEVAL-IFN003V1 pmsm foc motor driver based on the l6230 and stm32f103 features input range: 8 v up to 48 v (up to 45 w) stmicroelectronics? arm ? cortex-m3 core- based stm32f103 microcontroller dmos fully integrated three-phase motor driver l6230 in a powerso package four-layer board sensorless and hall sensors/encoder current sensing mode: single-shunt resistor compatible with new ve rsion of stm32 foc firmware library: stm 32 pmsm foc sdk v3.0 debug connector usb interface for real-time data exchange rohs compliant description the STEVAL-IFN003V1 demonstration board is based on stmicroelectronics? arm ? cortex-m3 core-based stm32f103 microcontroller and the dmos fully integrated three-phase motor driver l6230 implementing field-oriented control of a pmsm motor. the board is designed as an evaluation environment for motor control applications in the range of 8 v - 48 v of dc bus voltage and up to 45 w, exploiting the computational power of the stm32f103. this microcontroller features internal 20 kb sram and 128 kb flash, and swd debugging. the l6230 dmos driver features 2.8 a output peak current, non- dissipative overcurrent detection/protection, cross-conduction protection, uncommitted comparator, thermal shutdown and undervoltage lockout. the STEVAL-IFN003V1 is provided with a specific usb interface for the real-time data exchange. offering dedicated hardware evaluation features, the STEVAL-IFN003V1 board is designed to help developers evaluate the device and develop their own applications. the STEVAL-IFN003V1 can be used together with the stm32 pmsm single/dual foc sdk v3.0 and constitutes a complete motor control evaluation and development platform. www.st.com
schematic circuit STEVAL-IFN003V1 2/5 doc id 022383 rev 1 1 schematic circuit figure 1. schematic (part 1) ! - v " ) # ) ; ) ! p p l i c a t i o n r e f e r e n c e / 5 4 / 5 4 / 5 4 2 3 2 8 7 2 3 2 8 7 2 3 2 8 7 ' , $ * ( 1 % 8 6 b ) % . % 8 6 b ) % . , 1 , 1 , 1 ( 1 ( 1 ( 1 2 3 2 8 7 2 3 2 8 7 2 3 2 8 7 6 ( 1 6 ( 6 ( 1 6 ( 6 ( 1 6 ( 6 ( 1 6 ( ' , $ * ( 1 , 1 ( 1 , 1 ( 1 , 1 ( 1 6 ( 1 6 ( 6 ( 1 6 ( ( q f % ( q f = ( q f $ ( q f $ ( q f = ( q f % ' $ & b 2 8 7 ' $ & b 2 8 7 8 6 $ 5 7 b 7 ; 6 : 2 8 6 $ 5 7 b 5 ; 6 : ' , 2 6 : & / . 6 3 ( ( ' & 3 & 3 & 3 2 8 7 5 ( 6 ( 7 6 7 $ 5 7 9 ' $ & b 2 8 7 9 ' $ & b 2 8 7 9 6 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 6 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 9 ' ' b 0 & 8 5 . 5 . & q ) 9 & q ) 9 5 n 5 n 5 5 & q ) 9 & q ) 9 5 5 5 1 0 5 1 0 & q ) 9 & q ) 9 8 & , & 7 6 9 $ , ' 7 6 6 2 3 8 & , & 7 6 9 $ , ' 7 6 6 2 3 8 6 7 0 ) & % 7 8 6 7 0 ) & % 7 3 $ : . 8 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 & 3 & 3 ' 2 6 & , 1 3 ' 2 6 & 2 8 7 1 5 6 7 % 2 2 7 9 % $ 7 9 6 6 $ 9 6 6 9 6 6 9 6 6 9 ' ' $ 9 ' ' 9 ' ' 9 ' ' 3 & 7 $ 0 3 5 7 & - 3 - 3 5 n 5 n 5 n 5 n 5 5 5 n 5 n - 8 / 3 ' - 8 / 3 ' * 1 ' * 1 ' 9 & 3 9 % 2 2 7 6 ( 1 6 ( 6 ( 1 6 ( 6 ( 1 6 ( 2 8 7 2 8 7 2 8 7 , 1 , 1 , 1 ( 1 ( 1 ( 1 & 3 & 3 ' , $ * ( 1 & 3 2 8 7 ( 3 ( 3 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & * 1 ' 1 & * 1 ' 9 6 $ 9 6 % & s ) 9 & s ) 9 & q ) 9 & q ) 9 & x ) 9 & x ) 9 5 n 5 n - 3 - 3 & q ) 9 & q ) 9 & s ) 9 & s ) 9 ; 0 + ] z l w k v r f n h w ; 0 + ] z l w k v r f n h w 5 n 5 n & q ) 9 & q ) 9 & q ) 9 & q ) 9 5 n 5 n ' % $ 9 ' % $ 9 & q ) 9 & q ) 9 5 : 5 : 5 n 5 n & s ) 9 & s ) 9 5 n 5 n 5 n 5 n & x ) 9 & x ) 9 5 n 5 n - 3 - 3 & s ) 9 & s ) 9 5 5 - 3 - 3 5 n 5 n 5 n 5 n & q ) 9 & q ) 9 5 1 0 5 1 0 5 : 5 : 8 $ , & 7 6 9 $ , ' 7 6 6 2 3 8 $ , & 7 6 9 $ , ' 7 6 6 2 3 5 n 5 n - 3 - 3 & q ) 9 & q ) 9 & s ) 9 & s ) 9 5 n 5 n & q ) 9 & q ) 9 5 5 - 3 - 3 5 n 5 n & 1 & 2 1 & 1 & 2 1 5 5 5 : 5 : & s ) 9 & s ) 9 & s ) 9 & s ) 9 5 n 5 n 5 1 0 5 1 0 5 . 5 . - 6 7 5 , 3 3 0 - 6 7 5 , 3 3 0 8 % , & 7 6 9 $ , ' 7 6 6 2 3 8 % , & 7 6 9 $ , ' 7 6 6 2 3 5 n 5 n & q ) 9 & q ) 9 5 5 5 n 5 n 5 n 5 n & s ) 9 & s ) 9 5 n 5 n
STEVAL-IFN003V1 schematic circuit doc id 022383 rev 1 3/5 figure 2. schematic (part 2) ! - v 2 % 3 % 4 3 4 ! 2 4 3 4 / 0 3 0 % % $ # 0 # 0
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revision history STEVAL-IFN003V1 4/5 doc id 022383 rev 1 2 revision history table 1. document revision history date revision changes 20-oct-2011 1 initial release.
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